In semiconductor fabrication, standard cell methodology typically involves designing integrated circuits having various functionality using standard components and interconnected structures. A standard cell can be made up of a group of transistor structures, passive structures, and interconnect structures that make up, e.g., logic functions, storage functions, or the like.
As integrated circuits continue to become smaller and simultaneously comprise an increasing number of electronic components within a given area, there is a desire for reducing the footprint of the devices and thus the size of the standard cell. However, as the devices become smaller, they also become more difficult to access by electrical interconnects.
Thus, there is a need for improved technologies providing smaller devices that still are easy to access and integrate in integrated circuit architectures.